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PRELIMINARY
W167B
133-MHz Spread Spectrum FTG for Pentium(R) II Platforms
Features
* Maximized EMI Suppression using Cypress's Spread Spectrum technology * Three copies of CPU outputs selectable frequency * Three copies of 3V66 selectable frequency output at 3.3V * Ten copies of PCI clocks (selectable frequency), 3.3V * One double strength 14.318-MHz reference output at 3.3V * One copy of 48-MHz USB clock * One copy of selectable 24-/48-MHz for SIO * One copy of CPU-divide-by-2 output as reference input to Direct RambusTM Clock Generator (Cypress W134) * Three copies of IOAPIC * Available in 48-pin SSOP (300 mils) Duty Cycle: ................................................................ 45/55% Spread Spectrum Modulation:................................... 0.25% CPU to 3V66 Output Offset: ............. 0.0-1.5 ns (CPU leads) 3V66 to PCI Output Offset:.............. 1.5-4.0 ns (3V66 leads) CPU to IOAPIC Output Offset: ......... 1.5-4.0 ns (CPU leads) Table 1. Pin Selectable Frequency SEL133/ CPU 100# SEL2 SEL1 SEL0 MHz 1 1 1 1 133.3 1 1 1 0 138 1 1 0 1 143 1 1 0 0 148 1 0 1 1 150 1 0 1 0 152.5 1 0 0 1 155 1 0 0 0 160 0 1 1 1 100.2 0 1 1 0 105 0 1 0 1 114 0 1 0 0 120 0 0 1 1 66.8 0 0 1 0 124 0 0 0 1 128.5 0 0 0 0 133.9 3V66 MHz 66.7 69 71.5 74 75 76.3 77.5 80 66.8 70 76 80 66.8 82.7 64.3 67 PCI IOAPIC MHz MHz 33.3 16.7 34.5 17.3 35.8 17.9 37 18.5 37.5 18.8 38.1 19.1 38.8 19.4 40 20 33.4 16.7 35 17.5 38 19 40 20 33.4 16.7 41.3 20.7 32.1 16.1 33.5 16.7
Key Specifications
Supply Voltages: ...................................... VDDQ2 = 2.5V5% VDDQ3 = 3.3V5% CPU, CPUdiv2 Output Jitter:....................................... 250 ps CPU, CPUdiv2 Output Skew: ...................................... 175 ps IOAPIC, 3V66 Output Skew: ....................................... 250 ps PCI0:8 Pin to Pin Skew: .............................................. 500 ps
Block Diagram
VDDQ3 X1 X2
Pin Configuration
REF2X
[1]
XTAL OSC
VDDQ2 CPU_[0:2]
3
/2 SEL133/100#
CPUdiv2 VDDQ3
PLL 1
/2//1.5
3V66_[0:2] 3
PCI0/SEL2* PCI1/SEL1* /2 8 PCI_[2:9]
PWRDWN#
Power Down Logic
VDDQ2
/2 3 IOAPIC[0:2]
IOAPIC2 REF2X VDDQ3 X1 X2 GND SEL2*/PCI0 SEL1*/PCI1 VDDQ3 PCI2 PCI3 PCI4 PCI5 GND PCI6 PCI7 VDDQ3 PCI8 PCI9 GND 3V66_0 3V66_1 3V66_2 VDDQ3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
GND VDDQ2 IOAPIC0 IOAPIC1 GND VDDQ2 CPUdiv2 GND VDDQ2 CPU2 GND VDDQ2 CPU1 CPU0 SDATA VDDQ3 GND PWRDN#* SCLK VDDQ3
Q# VDDQ3
PLL2 48MHz/SEL0*
Note: 1. Internal 250-k pull-up resistors present on inputs marked with *. Design should not rely solely on internal pull-up resistor to set I/O pins HIGH.
W167B
SIO/24_48#MHz*
48MHz/SEL0* GND SEL133/100#
SDATA SCLK
/2
Serial Logic
SIO/24_48#MHz
Direct Rambus is a trademark of Rambus, Inc. Pentium is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
* 408-943-2600 November 2, 1999
PRELIMINARY
Pin Definitions
Pin Name CPU0:2 SEL133/100# PCI0/SEL2 Pin No. 35, 36, 39 25 7 Pin Type O I I/O Pin Description
W167B
CPU Clock Outputs 0 through 2: CPU clock outputs. Their output voltage swing is controlled by voltage applied to VDDQ2. SEL133/100#: Frequency selection input pin as shown in Table 1. PCI Clock Output 0 and Selection Bit 2: As an output, this pin works in conjunction with PCI2:9. When an input, this pin functions as part of the frequency selection address (see Table 1). PCI Clock Output 1 and Selection Bit 1: As an output, this pin works in conjunction with PCI2:9. When an input, this pin functions as part of the frequency selection address (see Table 1). PCI Clock Outputs 2 through 9: Output voltage swing is controlled by voltage applied to VDDQ3. 66-MHz Clock Outputs 0 through 2: Output voltage swing is controlled by voltage applied to VDDQ3. CPU-Divide-By-2 Output: This serves as a reference input signal for Direct Rambus Clock Generator (Cypress W134). The output voltage is determined by VDDQ2. I/O APIC Clock Output 0 through 2: Provide outputs synchronous to CPU clock. See Table 1 and Table 5 for their relation to other system clock outputs. 48-MHz Output and Selection Bit 0: Fixed clock output that defaults to 48-MHz following device power-up. When an input, this pin functions as part of the frequency selection address (see Table 1). Super I/O Reference Clock Output and SIO Clock Frequency Select: Fixed clock output that provides the reference input clock to a Super I/O device. The output frequency is determined by the input value on this pin during power up. If input is sampled HIGH, the output operates at 24 MHz, otherwise, the output operates at 48 MHz. Fixed 14.318-MHz Output: With double strength driving capability. Power Down Control Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Serial Data Input: Data input for Serial Data Interface. Refer to Serial Data Interface section that follows. Serial Clock Input: Clock input for Serial Data Interface. Refer to Serial Data Interface section that follows. Power Connection: Connected to 2.5V power supply. Power Connection: Connected to 3.3V supply. Ground Connection: Connect all ground pins to the common system ground plane.
PCI1/SEL1
8
I/O
PCI2:9
10, 11, 12, 13, 15, 16, 18, 19 21, 22, 23 42
O
3V66_0:2 CPUdiv2
O O
IOAPIC0:2 48MHZ/SEL0
46, 45, 1 27
O I/O
SIO/24_48#MHz
28
I/O
REF2X PWRDWN# X1
2 31 4
O I I
X2 SDATA SCLK VDDQ2 VDDQ3 GND
5 34 30 37, 40, 43, 47 3, 9, 17, 24, 29, 33 6, 14, 20, 26, 32, 38, 41, 44, 48
I I/O I P P G
2
PRELIMINARY
Overview
The W167B, a motherboard clock synthesizer, provides 2.5V CPU clock outputs for advanced CPU and a CPU-divide-by-2 reference frequency for Direct Rambus Clock Generator (such as Cypress W134) interface. Fixed output frequencies are provided for other system functions. I/O Pin Operation Pins 7, 8, 27, and 28 are dual-purpose l/O pins. Upon powerup these pins act as logic inputs, allowing the determination of assigned device functions. A short time after power-up, the logic state of these pins is latched and the pins then become clock outputs. This feature reduces device pin count by combining clock outputs with input select pins. An external 10-k "strapping" resistor is connected between each l/O pin and ground or VDD3. Connection to ground sets a latch to "0", connection to V DD3 sets a latch to "1". Figure 1 and Figure 2 show two suggested methods for strapping resistor connection. Upon W167B power up, the first 2 ms of operation is used for input logic selection. During this period, these dual-purpose I/O pins are three-stated, allowing the output strapping resistor
W167B
on each l/O pin to pull the pin and its associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic 0 or 1 condition of each l/O pin is then latched. Next, the output buffers are enabled, converting the l/O pins into operating clock outputs. The 2-ms timer starts when VDD reaches 2.0V. The input bits can only be reset by turning VDD off and then back on again. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of the clock outputs is <40 (nominal) which is minimally affected by the 10-k strap to ground or VDD. As with the series termination resistor, the output strapping resistor should be placed as close to the l/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDD should be kept less than two inches in length to prevent system noise coupling during input logic sampling. When the clock outputs are enabled following the 2-ms input period, target (normal) output frequency is delivered assuming that VDD has stabilized. If VDD has not yet reached full value, output frequency initially may be below target but will increase to target once VDD voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled.
VDD Output Strapping Resistor Series Termination Resistor R Clock Load
10 k (Load Option 1) W167B Output Buffer Power-on Reset Timer Output Three-state Hold Output Low
D
10 k (Load Option 0)
Q
Data Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Jumper Options
VDD 10 k W167B Output Buffer Power-on Reset Timer Output Three-state Hold Output Low
D
Output Strapping Resistor Series Termination Resistor R Clock Load
Q
Data Latch
Figure 2. Input Logic Selection Through Jumper Option
3
PRELIMINARY
CPU/PCI Frequency Selection CPU frequency is selected with I/O pins 7, 8, 27, (SEL2/PCI0, SEL1/PCI1, 48MHz/SEL0, respectively) and input pin 25 (SEL133/100#). Refer to Table 1 for CPU/PCI frequency programming information. Additional frequency selections are available through the serial data interface. Refer to Table 5 on page 9. Output Buffer Configuration Clock Outputs All clock outputs are designed to drive serial terminated clock lines. The W167B outputs are CMOS-type which provide railto-rail output swing. Crystal Oscillator
W167B
The W167B requires one input reference clock to synthesize all output frequencies. The reference clock can be either an externally generated clock signal or the clock generated by the internal crystal oscillator. When using an external clock signal, pin X1 is used as the clock input and pin X2 is left open. The internal crystal oscillator is used in conjunction with a quartz crystal connected to device pins X1 and X2. This forms a parallel resonant crystal oscillator circuit. The W167B incorporates the necessary feedback resistor and crystal load capacitors. Including typical stray circuit capacitance, the total load presented to the crystal is approximately 18 pF. For optimum frequency accuracy without the addition of external capacitors, a parallel-resonant mode crystal specifying a load of 18 pF should be used. This will typically yield reference frequency accuracies within 100 ppm.
4
PRELIMINARY
Spread Spectrum Feature
The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 3. As shown in Figure 3, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is dB = 6.5 + 9*log10(P) + 9*log10(F)
W167B
Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The output clock is modulated with a waveform depicted in Figure 4. This waveform, as discussed in "Spread Spectrum Clock Generation for the Reduction of Radiated Emissions" by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is -0.5% downspread. Figure 4 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices.
EMI Reduction
Spread Spectrum Enabled NonSpread Spectrum
Figure 3. Typical Clock and SSFTG Comparison
100% 80% 60% 40% 20% 0% -20% -40% -60% -80% -100%
Frequency Shift
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
Time
Figure 4. Typical Modulation Profile
5
100%
PRELIMINARY
Serial Data Interface
The W167B features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Upon power-up, the W167B initializes with default register settings, therefore the use of this serial data interface is optional. The serial interface is write-only (to the clock chip) and is the dedicated function of device pins Table 2. Serial Data Interface Control Functions Summary Control Function Clock Output Disable Description Common Application
W167B
SDATA and SCLOCK. In motherboard applications, SDATA and SCLOCK are typically driven by two logic outputs of the chipset. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Table 2 summarizes the control functions of the serial data interface.
Any individual clock output(s) can be disabled. Dis- Unused outputs are disabled to reduce EMI abled outputs are actively held LOW. and system power. Examples are clock outputs to unused SDRAM DIMM socket or PCI slot. Provides CPU/PCI frequency selections. Frequency is changed in a smooth and controlled fashion. For alternate CPU devices, and power management options. Smooth frequency transition allows CPU frequency change under normal system operation. Production PCB testing. Production PCB testing.
CPU Clock Frequency Selection
Output Three-state Test Mode (Reserved) Operation
Puts all clock outputs into a high-impedance state. All clock outputs toggle in relation with X1 input, internal PLL is bypassed. Refer to Table 4.
Reserved function for future device revision or pro- No user application. Register bit must be writduction device testing. ten as 0.
Data is written to the W167B in ten bytes of eight bits each. Bytes are written in the order shown in Table 3. Table 3. Byte Writing Sequence Byte Sequence 1 Byte Name Slave Address Bit Sequence 11010010 Byte Description Commands the W167B to accept the bits in Data Bytes 0-6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W167B is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). Unused by the W167B, therefore bit values are ignored (don't care). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. Unused by the W167B, therefore bit values are ignored (don't care). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. The data bits in these bytes set internal W167B registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 4, Data Byte Serial Configuration Map.
2
Command Code
Don't Care
3
Byte Count
Don't Care
4 5 6 7 8 9 10
Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6
Refer to Table 4
6
PRELIMINARY
Writing Data Bytes Each bit in the data bytes control a particular device function except for the "reserved" bits which must be written as a logic 0. Bits are written MSB (most significant bit) first, which is bit Table 4. Data Bytes 0-6 Serial Configuration Map Affected Pin Bit(s) 7 6 5 4 3 2 1-0 Data Byte 1 7 6 5 4 3 2 1 0 Data Byte 2 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 16 15 13 12 11 10 8 7 -23 22 21 --19 18 PCI7 PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 -3V66_2 3V66_1 3V66_0 --PCI9 PCI8 Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable (Reserved) (Reserved) Clock Output Disable Clock Output Disable Low Low Low Low Low Low Low Low -Low Low Low --Low Low Active Active Active Active Active Active Active Active -Active Active Active --Active Active 27 28 -42 -39 36 35 48MHz 24/48MHz -CPUdiv2 -CPU2 CPU1 CPU0 Clock Output Disable Clock Output Disable (Reserved) Clock Output Disable (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable Low Low -Low -Low Low Low Active Active -Active -Active Active Active Pin No. -------Pin Name -------Control Function SEL133/100# SEL2 SEL1 SEL0 Frequency Table Selection (Reserved) Functional control 0 Refer to Table 5 Refer to Table 5 Refer to Table 5 Refer to Table 5 Controlled by external pin (per Table 1) -Refer to Table 6 Controlled by BYTE0 (per Table 5) -Data Byte 0 Bit Control 1
W167B
7. Table 4 gives the bit formats for registers located in Data Bytes 0-6. Table 5 details additional frequency selections that are available through the serial data interface. Table 6 details the select functions for Byte 0, bits 1 and 0.
Default 0 0 0 0 0 0 00 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 1 1
Data Byte 3
7
PRELIMINARY
Table 4. Data Bytes 0-6 Serial Configuration Map (continued) Affected Pin Bit(s) 7 6 5 4 3 2 1 0 Data Byte 5 --------Data Byte 6 ------------------------(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) --------------------------------(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) ----------------Pin No. -1 45 46 ---2 Pin Name -IOAPIC2 IOAPIC1 IOAPIC0 ---REF2X Control Function (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable (Reserved) (Reserved) (Reserved) Clock Output Disable 0 -Low Low Low ---Low Data Byte 4 -Active Active Active ---Active Bit Control 1
W167B
Default 0 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
8
PRELIMINARY
Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes SEL133/100# 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 SEL2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 SEL1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 SEL0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 CPU MHz 133.3 138 143 148 150 152.5 155 160 100.2 105 114 120 66.8 124 128.5 133.9 3V66 MHz 66.7 69 71.5 74 75 76.3 77.5 80 66.8 70 76 80 66.8 82.7 64.3 67 PCI MHz 33.3 34.5 35.8 37 37.5 38.1 38.8 40 33.4 35 38 40 33.4 41.3 32.1 33.5
W167B
IOAPIC MHz 16.7 17.3 17.9 18.5 18.8 19.1 19.4 20 16.7 17.5 19 20 16.7 20.7 16.1 16.7
Table 6. Select Function for Data Byte 0, Bits 0:1 Input Conditions Data Byte 0 Function Normal Operation Test Mode Spread Spectrum Three-state Bit 1 0 0 1 1 Bit 0 0 1 0 1 CPU0:2, Note 2 TBD 0.25% Hi-Z PCI0:9 Note 2 TBD 0.25% Hi-Z REF2X 14.318 MHz TBD 14.318 MHz Hi-Z IOAPIC0:2 Note 2 TBD 0.25% Hi-Z 48/24MHZ 48/24 MHz TBD 48/24 MHz Hi-Z Output Conditions
Note: 2. CPU, IOAPIC, and PCI frequency selections are listed in Table 1 and Table 5.
9
PRELIMINARY
How To Use the Serial Data Interface
Electrical Requirements Figure 5 illustrates electrical characteristics for the serial interface bus used with the W167B. Devices send data over the bus with an open drain logic output that can (a) pull the bus line LOW, or (b) let the bus default to logic 1. The pull-up resistors on the bus (both clock and data lines) establish a default logic 1. All bus devices generally have logic inputs to receive data.
VDD
W167B
Although the W167B is a receive-only device (no data writeback capability), it does transmit an "acknowledge" data pulse after each byte is received. Thus, the SDATA line can both transmit and receive data. The pull-up resistor should be sized to meet the rise and fall times specified in AC parameters, taking into consideration total bus line capacitance.
VDD
~ 2k SERIAL BUS DATA LINE SERIAL BUS CLOCK LINE
~ 2k
SDCLK CLOCK IN CLOCK OUT N DATA IN DATA OUT
SDATA CLOCK IN N
SCLOCK DATA IN DATA OUT
SDATA
N
CHIP SET (SERIAL BUS MASTER TRANSMITTER)
CLOCK DEVICE (SERIAL BUS SLAVE RECEIVER)
Figure 5. Serial Interface Bus Electrical Characteristics
10
PRELIMINARY
Signaling Requirements As shown in Figure 6, valid data bits are defined as stable logic 0 or 1 condition on the data line during a clock HIGH (logic 1) pulse. A transitioning data line during a clock HIGH pulse may be interpreted as a start or stop pulse (it will be interpreted as a start or stop pulse if the start/stop timing parameters are met). A write sequence is initiated by a "start bit" as shown in Figure 7. A "stop bit" signifies that a transmission has ended. As stated previously, the W167B sends an "acknowledge" pulse after receiving eight data bits in each byte as shown in Figure 8. Sending Data to the W167B
W167B
The device accepts data once it has detected a valid start bit and address byte sequence. Device functionality is changed upon the receipt of each data bit (registers are not double buffered). Partial transmission is allowed meaning that a transmission can be truncated as soon as the desired data bits are transmitted (remaining registers will be unmodified). Transmission is truncated with either a stop bit or new start bit (restart condition).
SDATA
SCLOCK
Valid Data Bit
Change of Data Allowed
Figure 6. Serial Data Bus Valid Data Bit
SDATA
SCLOCK Start Bit Stop Bit
Figure 7. Serial Data Bus Start and Stop Bit
11
Figure 8. Serial Data Bus Write Sequence
Signaling from System Core Logic Start Condition Slave Address (First Byte)
SDATA MSB 1 1 0 1 0 0 LSB 1 0 MSB
Stop Condition Command Code (Second Byte)
LSB
Byte Count (Third Byte)
MSB MSB
Last Data Byte (Last Byte)
LSB
SCLOCK
1
2
3
4
5
6
7
8
A
1
2
3
4
5
6
7
8
A
1
2
3
4
1
2
3
4
5
6
7
8
A
PRELIMINARY
SDATA
Signaling by Clock Device
Acknowledgment Bit from Clock Device
12 Figure 9. Serial Data Bus Timing Diagram
SDATA tSPF tLOW SCLOCK tSTHD tR tHIGH tF tDSU tDHD tSP tSPSU tSTHD t SPSU
W167B
PRELIMINARY
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions
.
W167B
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 0 to +70 -55 to +125 2 (min.) Unit V C C C kV
Parameter VDD, VIN TSTG TA TB ESDPROT
Description Voltage on any pin with respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias Input ESD Protection
DC Electrical Characteristics: TA = 0C to +70C, VDDQ3 = 3.3V5%, VDDQ2 = 2.5V5%
Parameter Supply Current IDD-3.3V IDD-2.5 VIL VIH IIL IIH IIL IIH Combined 3.3V Supply Current Combined 2.5V Supply Current Input Low Voltage Input High Voltage Input Low Current[4] Input High Current
[4] [4]
Description
Test Condition CPU0:3 =133 MHz[3] CPU0:3 =133 MHz
[3]
Min.
Typ.
Max. 160 90
Unit mA mA V V A A A A Unit mV V mA mA Unit mV V mA mA Unit mV V mA mA
Logic Inputs (All referenced to VDDQ3 = 3.3V) GND - 0.3 2.0 0.8 VDD + 0.3 -25 10 -5 5 Test Condition IOL = 1 mA IOH = -1 mA VOL = 1.25V VOH = 1.25V Test Condition IOL = 1 mA IOH = -1 mA VOL = 1.5V VOH = 1.5V Test Condition IOL = 1 mA IOH = -1 mA VOL = 1.5V VOH = 1.5V 3.1 70 65 100 95 145 135 3.1 45 45 Min. 65 65 Typ. 100 100 Max. 50 2.2 45 45 Min. 65 65 Typ. 100 100 Max. 50 Min. Typ. Max. 50
Input Low Current, SEL133/100#
Input High Current, SEL133/100#[4]
Clock Outputs CPU, CPUdiv2, IOAPIC (Referenced to VDDQ2) VOL VOH IOL IOH VOL VOH IOL IOH VOL VOH IOL IOH Output Low Voltage Output High Voltage Output Low Current Output High Current Output Low Voltage Output High Voltage Output Low Current Output High Current Output Low Voltage Output High Voltage Output Low Current Output High Current
48MHz, REF (Referenced to VDDQ3)
PCI, 3V66 (Referenced to VDDQ3)
Notes: 3. All clock outputs loaded with 6" 60 transmission lines with 20-pF capacitors. 4. W167B logic inputs have internal pull-up devices, except SEL133/100# (pull-ups not CMOS level).
13
PRELIMINARY
DC Electrical Characteristics: TA = 0C to +70C, VDDQ3 = 3.3V5%, VDDQ2 = 2.5V5% (continued)
Parameter Crystal Oscillator VTH CLOAD CIN,X1 CIN COUT LIN X1 Input Threshold Voltage[5] Load Capacitance, Imposed on External Crystal[6] X1 Input Capacitance[7] Input Pin Capacitance Output Pin Capacitance Input Pin Inductance Pin X2 unconnected Except X1 and X2 1.65 18 28 5 6 7 Description Test Condition Min. Typ. Max.
W167B
Unit V pF pF pF pF nH
Pin Capacitance/Inductance
3.3V AC Electrical Characteristics
TA = 0C to +70C, VDDQ3 = 3.3V5%,VDDQ2 = 2.5V 5% fXTL = 14.31818 MHz Spread Spectrum function turned off AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output.[8] 3V66 Clock Outputs, 3V66_0:2 (Lump Capacitance Test Load = 30 pF) Parameter f tR tF tD fST Description Frequency Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Note 9 Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 15 1 1 45 Test Condition/Comments Min. Typ. 66.6 4 4 55 3 Max. Unit MHz V/ns V/ns % ms
Zo
Notes: 5. X1 input threshold voltage (typical) is VDD/2. 6. The W167B contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 18 pF; this includes typical stray capacitance of short PCB traces to crystal. 7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). 8. Period, jitter, offset, and skew measured on rising edge at 1.5V. 9. 3V66 is CPU/2 for CPU =133 MHz and (2 x CPU)/3 for CPU = 100 MHz.
14
PRELIMINARY
PCI Clock Outputs, PCI0:9 (Lump Capacitance Test Load = 30 pF Parameter tP tH tL tR tF tD tJC tSK tO fST Description Period High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Output Skew 3V66 to PCI Clock Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Measured on rising edge at 1.5V
[10]
W167B
Min. 30 12 12 1 1 45
Typ.
Max.
Unit ns ns ns
Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Covers all 3V66/PCI outputs. Measured on rising edge at 1.5V. 3V66 leads PCI output. Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value.
4 4 55 500 500
V/ns V/ns % ps ps ns ms
1.5
4 3
Zo
15
REF Clock Outputs, REF0:1 (Lump Capacitance Test Load = 20 pF) Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 25 0.5 0.5 45 Min. Typ. 14.318 2 2 55 3 V/ns V/ns % ms Max. Unit
Zo
48-MHZ Clock Output (Lump Capacitance Test Load = 20 pF) Parameter f fD m/n tR tF tD fST Description Frequency, Actual Deviation from 48 MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Determined by PLL divider ratio (see m/n below) (48.008 - 48)/48 (14.31818 MHz x 57/17 = 48.008 MHz) Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 25 0.5 0.5 45 Min. Typ. 48.008 +167 57/17 2 2 55 3 V/ns V/ns % ms Max. Unit MHz ppm
Zo
Note: 10. PCI clock is CPU/4 for CPU = 133 MHz and CPU/3 for CPU = 100 MHz.
15
PRELIMINARY
2.5V AC Electrical Characteristics
TA = 0C to +70C, VDDQ3 = 3.3V5%, V DDQ2= 2.5V5% fXTL = 14.31818 MHz Spread Spectrum function turned off
W167B
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output.[11] CPU Clock Outputs, CPU0:2 (Lump Capacitance Test Load = 20 pF) CPU = 133 MHz Parameter tP tH tL tR tF tD tJC Description Period High Time Low Time Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition/Comments Measured on rising edge at 1.25V Duration of clock cycle above 2.0V Duration of clock cycle below 0.4V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 20 7.5 1.87 1.67 1 1 45 4 4 55 250 7.65 CPU = 100 MHz Typ. Max. Unit 10.2 ns ns ns 4 4 55 250 V/ns V/ns % ps 10 3.0 2.8 1 1 45 Min. Typ. Max. Min.
Output Rise Edge Rate Measured from 0.4V to 2.0V
tSK fST
Output Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance
175 3
175 3
ps ms
Zo
20
CPUdiv2 Clock Outputs, CPUdiv2 (Lump Capacitance Test Load = 20 pF) CPU = 133 MHz Parameter tP tH tL tR tF tD tJC Description Period High Time Low Time Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition/Comments Measured on rising edge at 1.25V Duration of clock cycle above 2.0V Duration of clock cycle below 0.4V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 20 15 5.25 5.05 1 1 45 4 4 55 250 15.3 CPU = 100 MHz Typ. Max. 20.4 Unit ns ns ns 4 4 55 250 V/ns V/ns % ps 20 7.5 7.3 1 1 45 Min. Typ. Max. Min.
Output Rise Edge Rate Measured from 0.4V to 2.0V
tSK fST
Output Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance
175 3
175 3
ps ms
Zo
20
Note: 11. Period, Jitter, offset, and skew measured on rising edge at 1.25V.
16
PRELIMINARY
IOAPIC Clock Output, IOAPIC (Lump Capacitance Test Load = 20 pF) Parameter f tR tF tD fST Description Frequency Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Note 12 Measured from 0.4V to 2.0V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 20 1 1 45 Test Condition/Comments Min Typ 16.67 4 4 55 3
W167B
Max
Unit MHz V/ns V/ns % ms
Zo
Note: 12. IOAPIC clock is CPU/8 for CPU = 133 MHz and CPU/6 for CPU = 100 MHz.
Ordering Information
Ordering Code W167B Document #: 38-00816 Package Name H Package Type 48-pin SSOP (300 mils)
17
PRELIMINARY
Package Diagram
48-Pin Small Shrink Outline Package (SSOP, 300 mils)
W167B
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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